H8SLASH3028F datasheet(453/923 Pages) RENESAS

453 / 923 page

Rev. 2.00, 09/03, page 423 of 890

11.2.9

TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a

group-by-group basis.

Bit

Initial value

Read/Write

G0CMS0

R/W

G0CMS1

R/W

G1CMS0

R/W

G1CMS1

R/W

G2CMS0

R/W

G2CMS1

R/W

G3CMS0

R/W

G3CMS1

R/W

Group 3 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 3

(TP15 to TP12)

Group 2 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 2

(TP11 to TP8)

Group 1 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 1

(TP7 to TP4)

Group 0 compare

match select 1 and 0

These bits select

the compare match

event that triggers

TPC output group 0

(TP3 to TP0)

TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits

select the compare match event that triggers TPC output group 3 (TP15 to TP12).

Bit 7

G3CMS1

Bit 6

G3CMS0

Description

TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit

timer channel 0

TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit

timer channel 1

TPC output group 3 (TP15 to TP12) is triggered by compare match in 16-bit

timer channel 2

TPC output group 3 (TP15 to TP12) is triggered by

compare match in 16-bit timer channel 2

(Initial value)

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