H8SLASH3028F datasheet(462/923 Pages) RENESAS

462 / 923 page

Rev. 2.00, 09/03, page 432 of 890

Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-

Overlapping Output): Figure 11.7 shows an example of the use of TPC output for four-phase

complementary non-overlapping pulse output.

GRB

H'0000

NDRB

PBDR

TP15

TP14

TP13

TP12

TP11

TP10

TP9

TP8

Time

TCNT

period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TISRA to enable

IMFA interrupts.

H'FF is written in PBDDR and NDERB, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in

TPCR to select compare match in the 16-bit timer channel set up in step 1 as the output trigger. Bits

G3NOV and G2NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in

NDRB.

TCNT value

Non-overlap margin

The 16-bit timer channel to be used as the output trigger channel is set up so that GRA and GRB are

output compare registers and the counter will be cleared by compare match B. The TPC output trigger

•

The timer counter in this 16-bit timer channel is started. When compare match B occurs, outputs change

from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed

by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRB.

Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95…

at successive IMFA interrupts. If the DMAC is set for activation by this interrupt, pulse output can be

obtained without loading the CPU.

GRA

Figure 11.7 Non-Overlapping TPC Output Example (Four-Phase Complementary

Non-Overlapping Pulse Output)

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