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H8/3028F Datasheet(PDF) 464 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 464 Page - Renesas Technology Corp |
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464 / 923 page ![]() Rev. 2.00, 09/03, page 434 of 890 11.4 Usage Notes 11.4.1 Operation of TPC Output Pins TP0 to TP15 are multiplexed with 16-bit timer, DMAC, address bus, and other pin functions. When 16-bit timer, DMAC, or address output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. 11.4.2 Note on Non-Overlapping Output During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare match A. 2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11.9 illustrates the non-overlapping TPC output operation. DDR NDER QQ TPC output pin DR NDR C QD QD Compare match A Compare match B Figure 11.9 Non-Overlapping TPC Output |
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