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H8/3028F Datasheet(PDF) 468 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 468 Page - Renesas Technology Corp |
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468 / 923 page  Rev. 2.00, 09/03, page 438 of 890 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the WDT. φ/2 φ/32 φ/64 φ/128 φ/256 φ/512 φ/2048 φ/4096 TCNT TCSR RSTCSR Reset control Interrupt signal Reset (internal, external) (interval timer) Interrupt control Overflow Clock Clock selector Read/ write control Internal data bus Internal clock sources RESO* Legend TCNT: TCSR: RSTCSR: Note: * Open-drain output pin Timer counter Timer control/status register Reset control/status register Figure 12.1 WDT Block Diagram 12.1.3 Pin Arrangement The pins*1 used by the watchdog timer are listed in table 12.1. Table 12.1 Name Abbreviation I/O Function Reset output RESO Output* 2 Outputs watchdog timer reset signal to external device Notes: 1. Not available on flash memory version. 2. Open drain output pin. |
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