H8SLASH3028F datasheet(472/923 Pages) RENESAS

472 / 923 page

Rev. 2.00, 09/03, page 442 of 890

12.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable and writable register used to monitor when a reset signal has been

generated by watchdog timer overflow, and to control external output of the reset signal.

Bit

Initial value

Read/Write

Notes: The procedure for writing to RSTCSR differs from that for other registers in order to

prevent its contents from being overwritten accidentally. For details see section 12.2.4,

Notes on Register Access.

* Only 0 can be written to bit 7, to clear the flag.

WRST

R/(W)*

RSTOE

R/W

—

Watchdog timer reset

Indicates that a reset signal has been generated

Reset output enable

Enables or disables output of the reset signal

to an external device

Reserved bits

Bits 7 and 6 are initialized by input of a reset signal to the

RES pin. They are not initialized by

reset signals generated by watchdog timer overflow.

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that

TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3028

Group chip internally. At the same time, if the RSTOE bit is set to 1, the reset signal is output

from the

RESO pin as low-level output to an external device, making it possible to reset the entire

system. Note that the flash memory version is not equipped with a

RESO pin.

Bit 7

WRST

Description

[Clearing conditions]

(Initial value)

• Reset signal at RES pin.

• Read WRST flag when WRST = 1, then write 0 to WRST.

[Setting condition]

Set when TCNT overflow generates a reset signal during watchdog timer operation

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