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H8/3028F Datasheet(PDF) 469 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 469 Page - Renesas Technology Corp |
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469 / 923 page ![]() Rev. 2.00, 09/03, page 439 of 890 12.1.4 Register Configuration Table 12.2 summarizes the WDT registers. Table 12.2 WDT Registers Address* 1 Write* 2 Read Name Abbreviation R/W Initial Value H'FFF8C H'FFF8C Timer control/status register TCSR R/(W)* 3 H'18 H'FFF8D Timer counter TCNT R/W H'00 H'FFF8E H'FFF8F Reset control/status register RSTCSR R/(W)* 3 H'3F Notes: 1. Lower 20 bits of the address in advanced mode. 2. Write word data starting at this address. 3. Only 0 can be written in bit 7, to clear the flag. 12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) TCNT is an 8-bit readable and writable up-counter. Bit Initial value Read/Write Note: TCNT is write-protected by a password. For details see section 12.2.4, Notes on Register Access. 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 0 0 R/W 2 0 R/W 1 0 R/W When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. |
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