H8SLASH3028F datasheet(473/923 Pages) RENESAS

473 / 923 page

Rev. 2.00, 09/03, page 443 of 890

Bit 6—Reset Output Enable (RSTOE): Enables or disables output of the reset signal from the

RESO pin when TCNT overflow generates a reset signal during watchdog timer operation. Note

that the flash memory version is not equipped with a

RESO pin.

Bit 6

RSTOE

Description

External output of reset signal disabled.

External output of reset signal enabled.

Bits 5 to 0—Reserved: These bits are reserved. They cannot be written to and are always read

as 1.

12.2.4

Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write. The procedures for writing and reading these registers are given below.

Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.

They cannot be written by byte instructions. Figure 12.2 shows the format of data written to

TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be

contained in the lower byte of the written word. The upper byte must contain H'5A (password for

TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT

or TCSR.

8 7

H'5A

Write data

Address

H'FFF8C*

8 7

H'A5

Write data

Address

H'FFF8C*

TCNT write

TCSR write

Note: * Lower 20 bits of the address in advanced mode.

Figure 12.2 Format of Data Written to TCNT and TCSR

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