H8SLASH3028F datasheet(470/923 Pages) RENESAS

470 / 923 page

Rev. 2.00, 09/03, page 440 of 890

12.2.2

Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable and writable register. Its functions include selecting the timer mode and

clock source.

Bit

Initial value

Read/Write

Notes: TCSR is write-protected by a password. For details see section 12.2.4, Notes on Register

Access.

* Only 0 can be written, to clear the flag.

OVF

R/(W)*

WT/IT

R/W

TME

R/W

—

CKS0

R/W

CKS2

R/W

CKS1

R/W

Overflow flag

Status flag indicating overflow

Clock select

These bits select the

TCNT clock source

Timer mode select

Selects the mode

Timer enable

Selects whether TCNT runs or halts

Reserved bits

Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a

reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values.

Bit 7—Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed

from H'FF to H'00.

Bit 7

OVF

Description

[Clearing condition]

Cleared by reading OVF when OVF = 1, then writing 0 in OVF

(Initial value)

[Setting condition]

Set when TCNT changes from H'FF to H'00

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