H8SLASH3028F datasheet(631/923 Pages) RENESAS

631 / 923 page

Rev. 2.00, 09/03, page 601 of 890

18.6.1

Program Mode

When writing data or programs to flash memory, the program/program-verify flowchart shown in

figure 18.10 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to flash memory without subjecting the device to

voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes

at a time.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of programming operations (N) are shown in table 21.19 in section 21.2.6,

Flash Memory Characteristics.

Following the elapse of (tsswe) µs or more after the SWE bit is set to 1 in FLMCR1, 128-byte data

is written consecutively to the write addresses. The lower 8 bits of the first address written to must

be H'00 and H'80, 128 consecutive byte data transfers are performed. The program address and

program data are latched in the flash memory. A 128-byte data transfer must be performed even if

writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.

Set a value greater than (tspsu + tsp + tcp + tcpsu) µs as the WDT overflow period. Preparation for

entering program mode (program setup) is performed next by setting the PSU bit in FLMCR1.

The operating mode is then switched to program mode by setting the P bit in FLMCR1 after the

elapse of at least (tspsu) µs. The time during which the P bit is set is the flash memory

programming time. Make a program setting so that the time for one programming operation is

within the range of (tsp) µs.

The wait time after P bit setting must be changed according to the degree of progress through the

programming operation. For details see “Notes on Program/Program-Verify Procedure.”

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