H8SLASH3028F datasheet(666/923 Pages) RENESAS

666 / 923 page

Rev. 2.00, 09/03, page 636 of 890

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software

standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal

operation. To clear this bit, write 0.

Bit 7

SSBY

Description

SLEEP instruction causes transition to sleep mode

(Initial value)

SLEEP instruction causes transition to software standby mode

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU

and on-chip supporting modules wait for the clock to settle when software standby mode is exited

by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to

the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See

table 20.3. If an external clock is used, set these bits so that the waiting time will be at least

100 µs.

Bit 6

STS2

Bit 5

STS1

Bit 4

STS0

Description

Waiting time = 8,192 states

(Initial value)

Waiting time = 16,384 states

Waiting time = 32,768 states

Waiting time = 65,536 states

Waiting time = 131,072 states

Waiting time = 262,144 states

Waiting time = 1,024 states

Illegal setting

Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and

bus control signals (

0 to CS7, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as

outputs or fixed high, or placed in the high-impedance state in software standby mode.

Bit 1

SSOE

Description

In software standby mode, the address bus and bus control signals are all high-

impedance

(Initial value)

In software standby mode, the address bus retains its output state and bus control

signals are fixed high

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