H8SLASH3028F datasheet(670/923 Pages) RENESAS

670 / 923 page

Rev. 2.00, 09/03, page 640 of 890

20.3

Sleep Mode

20.3.1

Transition to Sleep Mode

When the SSBY bit is cleared to 0 in SYSCR, execution of the SLEEP instruction causes a

transition from the program execution state to sleep mode. Immediately after executing the SLEEP

instruction the CPU halts, but the contents of its internal registers are retained. The DMA

controller (DMAC), DRAM interface, and on-chip supporting modules do not halt in sleep mode.

Modules which have been placed in standby by the module standby function, however, remain

halted.

20.3.2

Exit from Sleep Mode

Sleep mode is exited by an interrupt, or by input at the

RES or STBY pin.

Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt

exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting

module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by

an interrupt other than NMI if the interrupt is masked by interrupt priority settings and the settings

of the I and UI bits in CCR, IPR.

Exit by

RES

RES Input: Low input at the RES pin exits from sleep mode to the reset state.

Exit by

STBY

STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby

mode.

H8/3028F Datasheet(PDF) 670 Page - Renesas Technology Corp