H8SLASH3028F datasheet(669/923 Pages) RENESAS

669 / 923 page

Rev. 2.00, 09/03, page 639 of 890

Bit 6—Reserved: This bit can be written and read.

Bit 5—Module Standby L5 (MSTPL5): Selects whether to place the DRAM interface in

standby.

Bit 5

MSTPL5

Description

DRAM interface operates normally

(Initial value)

DRAM interface is in standby state

Bit 4—Module Standby L4 (MSTPL4): Selects whether to place the 16-bit timer in standby.

Bit 4

MSTPL4

Description

16-bit timer operates normally

(Initial value)

16-bit timer is in standby state

Bit 3—Module Standby L3 (MSTPL3): Selects whether to place 8-bit timer channels 0 and 1 in

standby.

Bit 3

MSTPL3

Description

8-bit timer channels 0 and 1 operate normally

(Initial value)

8-bit timer channels 0 and 1 are in standby state

Bit 2—Module Standby L2 (MSTPL2): Selects whether to place 8-bit timer channels 2 and 3 in

standby.

Bit 2

MSTPL2

Description

8-bit timer channels 2 and 3 operate normally

(Initial value)

8-bit timer channels 2 and 3 are in standby state

Bit 1—Reserved: This bit can be written and read.

Bit 0—Module Standby L0 (MSTPL0): Selects whether to place the A/D converter in standby.

Bit 0

MSTPL0

Description

A/D converter operates normally

(Initial value)

A/D converter is in standby state

H8/3028F Datasheet(PDF) 669 Page - Renesas Technology Corp