H8SLASH3028F datasheet(798/923 Pages) RENESAS

798 / 923 page

Rev. 2.00, 09/03, page 768 of 890

DRCRA—DRAM Control Register A

H'EE026

DRAM interface

DRAM area select

DRAS2 DRAS1 DRAS0

Area 5

Normal

DRAM space

(

Area 4

Normal

DRAM space

(

DRAM space

(

Area 3

Normal

DRAM space

(

DRAM space

(

DRAM space

(

Area 2

Normal

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space

(

DRAM space(

2)*

DRAM space(

4)*

DRAM space(

2)*

DRAM space(

2)*

Note:

* A single CSn pin serves as a common RAS output pin for a number of

areas. Unused

CSn pins can be used as input/output ports.

DRAS2

R/W

DRAS1

R/W

DRAS0

R/W

—

R/W

RDM

R/W

SRFMD

R/W

RFSHE

R/W

Bit

Initial value

Read/Write

Refresh pin enable

Self-refresh mode

RAS down mode

Burst access enable

RFSH pin refresh signal output is disabled

RFSH pin refresh signal output is enabled

DRAM self-refreshing is disabled in software standby mode

DRAM self-refreshing is enabled in software standby mode

DRAM interface: RAS up mode selected

DRAM interface: RAS down mode selected

Burst disabled (always full access)

DRAM space access performed in fast page mode

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