H8SLASH3028F datasheet(840/923 Pages) RENESAS

840 / 923 page

Rev. 2.00, 09/03, page 810 of 890

TCR2—Timer Control Register 2

H'FFF90

8-bit timer channel 2

TCR3—Timer Control Register 3

H'FFF91

8-bit timer channel 3

Bit

Initial value

Read/Write

R/W

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS2

R/W

CKS1

R/W

CKS0

Clock select 2 to 0

Clock input is disabled

Internal clock, counted on rising edge

φ/8

Internal clock, counted on rising edge

φ/64

Internal clock, counted on rising edge

φ/8192

External clock, counted on falling edge

External clock, counted on rising edge

External clock, counted on both

rising and falling edges

Counter clear 1 and 0

Clearing is disabled

Cleared by compare match A

Cleared by compare match B/input capture B

Cleared by input capture B

Timer overflow interrupt enable

OVI interrupt requested by OVF is disabled

OVI interrupt requested by OVF is enabled

Compare match interrupt enable A

CMIA interrupt requested by CMFA is disabled

CMIA interrupt requested by CMFA is enabled

Compare match interrupt enable B

CMIB interrupt requested by CMFB is disabled

CMIB interrupt requested by CMFB is enabled

CSK2 CSK1 CSK0

Description

Channel 2:

Count on TCNT3 overflow signal

Channel 3:

Count on TCNT2 compare match A

Note:

* If the clock input of channel 2 is the TCNT3 overflow

signal and that of channel 3 is the TCNT2 compare

match signal, no incrementing clock is generated.

Do not use this setting.

H8/3028F Datasheet(PDF) 840 Page - Renesas Technology Corp

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