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H8/3028F Datasheet(PDF) 910 Page - Renesas Technology Corp

Part # H8/3028F
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3028F Datasheet(HTML) 910 Page - Renesas Technology Corp

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Rev. 2.00, 09/03, page 880 of 890
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
1. To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the
RES signal low 10
system clock cycles before the
STBY signal goes low, as shown below. RES must remain low
until
STBY goes low (minimum delay from STBY low to RES high: 0 ns).
t1 ≥ 10tcyc
t2 ≥ 0 ns
STBY
RES
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR,
RES does not have to be
driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the
RES signal low approximately
100 ns before
STBY goes high.
STBY
RES
t
≥ 100 ns
tOSC



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