H8SLASH3028F datasheet(908/923 Pages) RENESAS

908 / 923 page

Rev. 2.00, 09/03, page 878 of 890

Modes 3 and 4: Figure D.2 is a timing diagram for the case in which

RES goes low during an

external memory access in mode 3 or 4. As soon as

RES goes low, all ports are initialized to the

input state.

AS, RD, HWR, LWR, and CS

0 go high, and D15 to D0 go to the high-impedance state.

The address bus is initialized to the low output level 2.5

φ clock cycles after the low level of RES

is sampled. However, when PA4 to PA6 are used as address bus pins, or when P83 to P81 and PB0

to PB3 are used as CS output pins, they go to the high-impedance state at the same time as RES

goes low. Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.

Access to external

memory

H'000000

High impedance

AS, RD

(read)

D15 to D0

(write)

HWR, LWR

(write)

Internal reset

signal

RES

P67/φ

I/O port,

PA4/A23 to PA6/A21,

CS7 to CS1

CS0

A20 to A0

Figure D.2 Reset during Memory Access (Modes 3 and 4)

Mode 5: Figure D.3 is a timing diagram for the case in which

RES goes low during an external

memory access in mode 5. As soon as

RES goes low, all ports are initialized to the input state. AS,

RD, HWR, and LWR go high, and the address bus and D

15 to D0 go to the high-impedance state.

Clock pin P67/φ goes to the output state at the next rise of φ after RES goes low.

H8/3028F Datasheet(PDF) 908 Page - Renesas Technology Corp