H8SLASH3028F datasheet(905/923 Pages) RENESAS

905 / 923 page

Rev. 2.00, 09/03, page 875 of 890

Name

Mode Reset

Hardware

Standby

Mode

Software Standby

Mode

Bus-Released

Mode

Program Execution

Mode

PB3

1 to 5 T

• RAS4 output*

(SSOE=0)

(SSOE=1)

• CS output*

(SSOE=0)

(SSOE=1)

• Otherwise*

Keep

• RAS4 output*

• CS output*

• Otherwise*

Keep

• RAS4 output

RAS4

• CS output

CS4

• Otherwise

I/O port

6, 7

Keep

—

I/O port

PB5 to

PB4

1 to 5 T

• CAS output*

(SSOE=0)

(SSOE=1)

• Otherwise*

Keep

• CAS output*

• Otherwise*

Keep

• CAS output

UCAS, LCAS

• Otherwise

I/O port

6, 7

Keep

—

I/O port

PB7 to

PB4

1 to 7 T

Keep

I/O port

RESO*1 —T*1

Legend

High

Low

High-impedance state

Keep: Input pins are in the high-impedance state; output pins maintain their previous state.

DDR: Data direction register

Notes: 1.

When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all

cleared to 0.

When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is

set to 1.

When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control

When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is

cleared to 0.

When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is

set to 1.

When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to

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