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H8/3028F Datasheet(PDF) 184 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 184 Page - Renesas Technology Corp |
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184 / 923 page  Rev. 2.00, 09/03, page 154 of 890 A23 to A0 φ CSn (RAS) Tp Tr Tc1 Tc2 ( UCAS/LCAS) PB4/PB5 AS RD (WE) D15 to D0 RD (WE) D15 to D0 ( UCAS/LCAS) PB4/PB5 Row Column Read access Write access Note: n = 2 to 5 High level High level Figure 6.18 Basic Access Timing (CSEL = 0 in DRCRB) 6.5.7 Precharge State Control In the H8/3028 Group, provision is made for the DRAM RAS precharge time by always inserting one RAS precharge state (Tp) when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit to 1 in DRCRB. The optimum number of Tp cycles should be set according to the DRAM connected and the operating frequency of the H8/3028 Group chip. Figure 6.19 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two Tp states are also used for CAS-before-RAS refresh cycles. |
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