H8SLASH3028F datasheet(185/923 Pages) RENESAS

Part #	H8/3028F

Description	Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

PDF	923 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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185 / 923 page

Rev. 2.00, 09/03, page 155 of 890

A23 to A0

CSn (RAS)

Tp1

Tc1

(

UCAS/LCAS)

PB4/PB5

RD (WE)

D15 to D0

RD (WE)

D15 to D0

(

UCAS/LCAS)

PB4/PB5

Tc2

Tp2

Note: n = 2 to 5

Row

High level

Column

Read access

Write access

Figure 6.19 Timing with Two Precharge States (CSEL = 0 in DRCRB)

6.5.8

Wait Control

In a DRAM access cycle, wait states can be inserted (1) between the Tr state and Tc1 state, and (2)

between the Tc1 state and Tc2 state.

Insertion of Trw Wait State between Tr and Tc1: One Trw state can be inserted between Tr and

Tc1 by setting the RCW bit to 1 in DRCRB.

Insertion of Tw Wait State(s) between Tc1 and Tc2: When the bit in ASTCR corresponding to an

area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the Tc1

state and Tc2 state by means of settings in WCRH and WCRL.

Figure 6.20 shows an example of the timing for wait state insertion.

H8/3028F Datasheet(PDF) 185 Page - Renesas Technology Corp