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H8/3002 Datasheet(PDF) 129 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 129 Page - Renesas Technology Corp |
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129 / 700 page  6.3.2 Chip Select Signals For each of areas 0 to 3, the H8/3002 can output a chip select signal (CS0 to CS3) that goes low to indicate when the area is selected. Figure 6-3 shows the output timing of a CSn signal (n = 0 to 3). Output of the CSn signal is enabled or disabled in the data direction register (DDR) of the corresponding port. A reset leaves pin CS0 in the output state and pins CS1 to CS3 in the input state. To output chip select signals CS1 to CS3, the corresponding DDR bits must be set to 1. For details see section 9, I/O Ports. The CSn signals are decoded from the address signals. They can be used as chip select signals for SRAM and other devices. Figure 6-3 CSn Output Timing (n = 0 to 3) Address bus n T T T 1 2 3 External address in area n ø CS 114 |
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