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H8/3002 Datasheet(PDF) 187 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 187 Page - Renesas Technology Corp |
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187 / 700 page  Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 7-22. Figure 7-22 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 7-9 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 7-9, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented. T1 T2 T3 RTCOR address NM N N + 1 ø Address bus RTCNT RTCOR RTCOR write cycle by CPU Internal write signal Compare match signal Inhibited RTCOR write data 172 |
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