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H8/3002 Datasheet(PDF) 190 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 190 Page - Renesas Technology Corp |
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190 / 700 page  7.4 Interrupt Source Compare match interrupts (CMI) can be generated when the refresh controller is used as an interval timer. Compare match interrupt requests are masked/unmasked with the CMIE bit of RTMCSR. 7.5 Usage Notes When using the DRAM or pseudo-static RAM refresh function, note the following points: • With the refresh controller, if directly connected DRAM or PSRAM is disconnected*, the P80/RFSH/IRQ0 pin and the P81/CS3/IRQ1 pin may both become low-level outputs simultaneously. Note: * When the DRAM enable bit (DRAME) or PSRAM enable bit (PSRAME) in the refresh control register (RFSHCR) is cleared to 0 after being set to 1. Figure 7-23 Operation when DRAM/PSRAM Connection is Switched 175 Address bus Area 3 start address P80/RFSH/IRQ0 P81/CS3/IRQ1 |
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