H8SLASH3002 datasheet(217/700 Pages) RENESAS

217 / 700 page

8.4.2 I/O Mode

I/O mode can be selected independently for each channel.

One byte or word is transferred at each transfer request in I/O mode. A designated number of

these transfers are executed. One address is specified in the memory address register (MAR), the

other in the I/O address register (IOAR). The direction of transfer is determined automatically

from the activation source. The transfer is from the address specified in IOAR to the address

specified in MAR if activated by an SCI channel 0 receive-data-full interrupt, and from the

address specified in MAR to the address specified in IOAR otherwise.

Table 8-6 indicates the register functions in I/O mode.

Table 8-6 Register Functions in I/O Mode

Function

Activated by

SCI Receive-

Data-Full

Other

Interrupt

Activation

Initial Setting

Operation

Destination

Source

Destination or

Incremented or

address

source address

decremented

once per transfer

Source

Destination

Source or

Held fixed

address

destination

address

Transfer counter

Number of

Decremented

transfers

once per

transfer until

H'0000 is

reached and

transfer ends

Legend

MAR:

Memory address register

IOAR: I/O address register

ETCR: Execute transfer count register

MAR and IOAR specify the source and destination addresses. MAR specifies a 24-bit source or

destination address, which is incremented or decremented as each byte or word is transferred.

IOAR specifies the lower 8 bits of a fixed address. The upper 16 bits are all 1s. IOAR is not

incremented or decremented.

Figure 8-2 illustrates how I/O mode operates.

MAR

All 1s

IOAR

ETCR

203

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