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H8/3002 Datasheet(PDF) 236 Page - Renesas Technology Corp |
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H8/3002 Datasheet(HTML) 236 Page - Renesas Technology Corp |
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236 / 700 page ![]() Figure 8-14 shows the timing when the DMAC is activated by low input at a DREQ pin. This example shows a word-size transfer from a 16-bit two-state access area to another 16-bit two-state access area. The DMAC continues the transfer while the DREQ pin is held low. Figure 8-14 Bus Timing of DMA Transfer Requested by Low DREQ Input ø DREQ RD HWR TEND T1 T2 T3 Td T1 T2 T1 T2 T1 T2 Td T1 T2 T1 T2 T1 T2 LWR , CPU cycle DMAC cycle CPU cycle DMAC cycle (last transfer cycle) CPU cycle Source address Destination address Source address Destination address Address bus 222 |
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