H8SLASH3002 datasheet(237/700 Pages) RENESAS

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H8/3002 Datasheet(PDF) 237 Page - Renesas Technology Corp

Part #	H8/3002

Description	Microcomputer

PDF	700 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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237 / 700 page

Figure 8-15 shows an auto-requested burst-mode transfer. This example shows a transfer of three

words from a 16-bit two-state access area to another 16-bit two-state access area.

Figure 8-15 Burst DMA Bus Timing

When the DMAC is activated from a

DREQ pin there is a minimum interval of four states from

when the transfer is requested until the DMAC starts operating. The

DREQ pin is not sampled

during the time between the transfer request and the start of the transfer. In short address mode

and normal mode, the pin is next sampled at the end of the read cycle. In block transfer mode, the

pin is next sampled at the end of one block transfer.

CPU cycle

DMAC cycle

Source

address

Destination

address

CPU cycle

Address

bus

HWR

LWR

223

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