H8SLASH3002 datasheet(241/700 Pages) RENESAS

241 / 700 page

8.4.9 Multiple-Channel Operation

The DMAC channel priority order is: channel 0 > channel 1 and channel A > channel B.

Table 8-12 shows the complete priority order.

Table 8-12 Channel Priority Order

Short Address Mode

Full Address Mode

Priority

Channel 0A

Channel 0

High

Channel 0B

Channel 1A

Channel 1

Channel 1B

Low

Multiple-Channel Operation: If transfers are requested on two or more channels simultaneously,

or if a transfer on one channel is requested during a transfer on another channel, the DMAC

operates as follows.

•

When a transfer is requested, the DMAC requests the bus right. When it gets the bus right, it

starts a transfer on the highest-priority channel at that time.

•

Once a transfer starts on one channel, requests to other channels are held pending until that

channel releases the bus.

•

After each transfer in short address mode, and each externally-requested or cycle-steal

transfer in normal mode, the DMAC releases the bus and returns to step 1. After releasing the

bus, if there is a transfer request for another channel, the DMAC requests the bus again.

•

After completion of a burst-mode transfer, or after transfer of one block in block transfer

mode, the DMAC releases the bus and returns to step 1. If there is a transfer request for a

higher-priority channel or a bus request from a higher-priority bus master, however, the

DMAC releases the bus after completing the transfer of the current byte or word. After

releasing the bus, if there is a transfer request for another channel, the DMAC requests the

bus again.

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H8/3002 Datasheet(PDF) 241 Page - Renesas Technology Corp