TMS320DM357 datasheet(7/195 Pages) TI

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2.2 Device Compatibility

2.3 ARM Subsystem

2.3.1

ARM926EJ-S RISC CPU

TMS320DM357

Digital Media System-on-Chip

www.ti.com

SPRS553 – NOVEMBER 2008

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In

general, the ARM is responsible for configuration and control of the device; including the Video and Image

Coprocessor (HMJCP), the VPSS Subsystem, and a majority of the peripherals and external memories.

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 8KB Data cache

• Write Buffer

• 16KB Internal RAM (32-bit wide access)

• 8KB Internal ROM (ARM bootloader for non-EMIFA boot options)

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

• PLL Controller

• Power and Sleep Controller (PSC)

• System Module

The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of

ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications

where full memory management, high performance, low die size, and low power are all important. The

ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to

trade off between high performance and high code density. Specifically, the ARM926EJ-S processor

supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,

providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code

overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data Caches

• Write buffer

• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

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