 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT89C51AC3-RDTIM Datasheet(PDF) 118 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT89C51AC3-RDTIM Datasheet(HTML) 118 Page - ATMEL Corporation |
|
|
118 / 140 page  118 AT89C51AC3 4383D–8051–02/08 Table 68. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = XXXX 0X0Xb bit addressable 7 6 5 4 3 2 1 0 - - - - SPIL - PADCL - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 SPIL SPI Interrupt Priority Level Less Significant Bit Refer to SPIH for priority level. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 PADCL ADC Interrupt Priority Level Less Significant Bit Refer to PSPIH for priority level. 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
