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COREPCI-AR Datasheet(PDF) 13 Page - Actel Corporation |
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COREPCI-AR Datasheet(HTML) 13 Page - Actel Corporation |
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13 / 42 page  CorePCI v5.41 v4.0 13 Read-Only Configuration Registers The read-only registers listed in Table 8 on page 13 have default values, but should be modified by the designer. See the PCI specification for setting these values: • Vendor ID • Device ID • Revision ID • Class Code • Subsystem ID • Subsystem Vendor ID The header type register is also read-only, but should not be modified (pre-set to a constant value of '00h'). The Capability Pointer is included when the HOT_SWAP_EN customization constant is set to '1'b. See Table 13 on page 16 for more information. Read/Write Configuration Registers The following registers have at least one bit that is both read and write capable. For a complete description, refer to the appropriate table. • "Command Register (04h)" (Table 9 on page 14) • " Status Register (06h)" (Table 10 on page 14) • "Memory Base Address Register Bit Definition (Locations 10h or 14h)" (Table 11 on page 16) • "I/O Base Address Register Bit Definitions (Location 14h Only)" (Table 12 on page 16) • "Interrupt Register (3Ch)" (Table 14 on page 16) • "Interrupt Control/Status Register (48h)" (Table 15 on page 16) • "Optional Hot-Swap Register (80h)" (Table 16 on page 16) Table 8 • PCI Configuration Header 31–24 23–16 15–8 7–0 Address Device ID Vendor ID 00h Status Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line Size 0Ch Base Address #0 (Memory Location for Baseline Target) 10h Base Address #1 (Optional Memory or I/O) 14h Base Address #2 (Optional I/O for DMA Register Mapping) 18h Base Address #3 1Ch Base Address #4 20h Base Address #5 24h CardBus CIS Pointer 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address 30h Reserved Capabilities Pointer 34h Reserved 38h Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch Interrupt Control/Status Register 48h Hot-Swap Register (optional) 80h |
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