CorePCI v5.41

v4.0

37

Notes:

1. Once CorePCI is granted the PCI bus, the core asserts DP_START and begins the process of enabling the bus to drive FRAMEn.

2. The PCI address and command are valid at the same time that FRAMEn is driven low.

3. Once FRAMEn is driven, if the backend is prepared to supply data, then IRDYn is asserted on the following cycle. The core can store

up to two DWORDs of data. If the Target has not responded with a TRDYn when the second DWORD is read, then the core will cease

reading as indicated by the RD_BE_NOW signal de-asserting.

4. The core then waits for the Target to complete the transfer by asserting TRDYn.

5. The transfer continues until either the transfer count is exhausted or the Target disconnects.

6. Cycle termination is initiated by driving FRAMEn high.

7. The number of clock cycles from DP_START to FRAMEn assertion can be increased by asserting STALL_MASTER.

Figure 22 • Zero-Wait-State DMA Master Write (Write to the PCI Bus)

CLK

FRAMEn

AD[31:0]

C_BE[3:0]

IRDYn

TRDYn

DEVSELn

PAR

STOPn

13

14

15

16

56

7

8

910

11

12

12

3

4

MEM_ADDRESS[23:2]

MEM_DATA[31:0]

RD_BE_NOW

RD_BE_RDY

DP_START

data3

data4

data5

data1

data2

data3

addr3

addr4

addr5

addr6

byte enables

Pd1

Pd2

Pd3

addr

Paddr

CMD

data0

add0

add1

add2

data0

data1

data2

Pd0

DP_DONE

RD_CYC

BARn_CYC