CorePCI v5.41

v4.0

39

When STALL_MASTER is active (see Figure 24), the core does not immediately assert FRAME and the PCI bus is idle. It is

possible for the PCI GNT to go away; in this case the core will stop the PCI transfer and assert DP_END.

Accessing the DMA Registers from the Backend

A write to the DMA register is accomplished by asserting

CS_CONTROLn, WR_CONTROLn, valid address, and valid

data at the same time. Registers can be updated one at a

time or in bursts by changing the address and data while

keeping CS_CONTROLn and WR_CONTROLn asserted

(Figure 25).

Reads from the DMA are pipelined with two cycles of

delay between valid address and valid data. To enable

the

output

drivers,

both

CS_CONTROLn

and

RD_CONTROLn must be driven low (Figure 26).

Figure 24 • DMA Master with STALL_MASTER Asserted

CLK

DP_START

STALL_MASTER

BUSY_MASTER

FRAMEn

AD[31:0]

CBE[3:0]

IRDYN

TRDYn

STOPn

DEVSELn

DP_DONE

RD_CYC

MEM_ADDRESS[23:2]

MEM_DATA[31:0]

RD_BE_RDY

RD_BE_NOW

addr

data0

data1

data2

CMD

byte enables

addr0

addr1

addr2

addr3

data0

data1

data2

Figure 25 • Backend Write to a DMA Register

Figure 26 • Backend Read from a DMA Register

CLK

WE_CONTROLn

CS_CONTROLn

CONTROL_ADD[1:0]

valid

MEM_DATA[31:0]

valid

12

3

4

CLK

CS_CONTROLn

WE_CONTROLn

CONTROL_ADD[1:0]

MEM_DATA[31:0]

valid

valid

1

2

34

56

78

910