COREPCI-AR datasheet(2/42 Pages) ACTEL

2 / 42 page

CorePCI v5.41

v4.0

General Description

CorePCI connects I/O, memory, and processor subsystem

resources to the main system via the PCI bus. CorePCI is

intended for use with a wide variety of peripherals

where high-performance data transactions are required.

Figure 1 on page 2 depicts typical system applications

using the baseline IP core. While CorePCI can handle any

transfer rate, most applications will operate at zero wait

states. When required, wait states can automatically be

inserted by a slower peripheral.

The core consists of up to four basic units: the Target

controller, the Master controller, the backend, and the

wrapper. Both the Target and Master controllers remain

constant for a variety of backends. A backend controller

provides the necessary control for the I/O or memory

subsystem and interfaces to the Target controller

through a generic interface. The wrapper combines the

Target and Master blocks with the backend for

implementation in a single Actel device.

CorePCI can be customized in two different ways. First, a

variety of variables are provided to easily change

parameters such as memory and I/O sizes. The second

method is to develop user-specific backend controllers

for non-standard peripherals.

Figure 1 • CorePCI System Block Diagram

MEM_ADDRESS BUS

MEM_DATA BUS

CorePCI

Target+Master

Controller

Memory

Subsystem

Sync SRAM

Sync DRAM

Optional

Memory or I/O

Subsystem

BAR1_ENABLE

Memory Control Signals

Master

Bridge

Target

FRAMEn

IRDYn

STOPn

DEVSELn

TRDYn

SERRn

IDSEL

PAR

CBE

PERRn

INTAn

CLK

RSTn

PCI Bus

REQn

GNTn

REQ64n

ACK64n

PAR64

System CPU

Master Control Signals

COREPCI-AR Datasheet(PDF) 2 Page - Actel Corporation

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