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OMAP3530-HiRel Datasheet(PDF) 31 Page - Texas Instruments |
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OMAP3530-HiRel Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 239 page  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors www.ti.com SPRS599 – JUNE 2009 Table 2-2. Ball Characteristics (CBC Pkg.) (continued) BALL BALL PIN MODE TYPE BALL BALL RESET POWER HYS BUFFER PULLUP IO BOTTOM TOP NAME [5] [6] RESET RESET REL. [10] [11] STRENG /DOWN CELL [1] [2] [4] STATE REL. MODE TH TYPE [14] [7] STATE [9] (mA) [13] [8] [12] - A12 sdrc_clk 0 IO L 0 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - D1 sdrc_d0 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - G1 sdrc_d1 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - G2 sdrc_d2 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - E1 sdrc_d3 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - D2 sdrc_d4 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - E2 sdrc_d5 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B3 sdrc_d6 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B4 sdrc_d7 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A10 sdrc_d8 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B11 sdrc_d9 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A11 sdrc_d10 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B12 sdrc_d11 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A16 sdrc_d12 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A17 sdrc_d13 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B17 sdrc_d14 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B18 sdrc_d15 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B7 sdrc_d16 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A5 sdrc_d17 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B6 sdrc_d18 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A6 sdrc_d19 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A8 sdrc_d20 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B9 sdrc_d21 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - A9 sdrc_d22 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B10 sdrc_d23 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - C21 sdrc_d24 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - D20 sdrc_d25 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - B19 sdrc_d26 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - C20 sdrc_d27 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - D21 sdrc_d28 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - E20 sdrc_d29 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS - E21 sdrc_d30 0 IO L Z 0 vdds_io Yes 4 (1) PU100/ LVDS/ PD100 CMOS Submit Documentation Feedback TERMINAL DESCRIPTION 31 |
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