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OMAP3530-HiRel Datasheet(PDF) 124 Page - Texas Instruments

Part # OMAP3530-HiRel
Description  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
PDF  239 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

OMAP3530-HiRel Datasheet(HTML) 124 Page - Texas Instruments

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5.2 Electrical Specifications Over Recommended Operating Conditions
OMAP3525-HiRel and OMAP3530-HiRel Applications Processors
SPRS599 – JUNE 2009
www.ti.com
(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted)
Table 5-2. DAC – Static Electrical Specification
PARAMETER
CONDITIONS/ASSUMPTIONS
MIN
TYP
MAX
UNIT
R
Resolution
10
Bits
DC ACCURACY
INL(1)
Integral nonlinearity
–1
1
LSB
DNL(2)
Differential nonlinearity
–1
1
LSB
ANALOG OUTPUT
-
Full-scale output voltage
RLOAD = 75 Ω
0,7
0.88
1
V
-
Output offset voltage
50
mV
-
Output offset voltage drift
20
mV/
°C
-
Gain error
–17
19
% FS
RVOUT
Output impedance
67.5
75
82.5
Ω
REFERENCE
VREF
Reference voltage range
0.525
0.55
0.575
V
-
Reference noise density
100-kHz reference noise
129
bandwidth
RSET
Full-scale current adjust resistor
3700
4000
4200
Ω
PSRR
Reference PSRR(3) (Up to 6 MHz)
40
dB
POWER CONSUMPTION
Ivdda-up
Analog Supply Current(4)
2 channels, no load
8
mA
-
Analog supply driving a 75-
Ω load
2 channels
50
mA
(RMS)
Ivdda-up (peak) Peak analog supply current:
Lasts less than 1 ns
60
mA
Ivdd-up
Digital supply current(5)
Measured at fCLK = 54 MHz, fOUT
2
mA
= 2 MHz sine wave, vdd = 1.3 V
Ivdd-up (peak)
Peak digital supply current(6)
Lasts less than 1 ns
2.5
mA
Ivdda-down
Analog power at power-down
T = 30
°C, vdda = 1.8 V
1.5
mA
Ivdd-down
Digital power at power-down
T = 30
°C, vdd = 1.3 V
1
mA
(1)
The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(2)
The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(3)
Assuming a capacitor of 0.1
µF at the tv_ref node.
(4)
The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK
(5)
The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.
(6)
The peak digital supply current occurs at full-scale transition for duration less than 1 ns.
VIDEO DAC SPECIFICATIONS
124
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