AT91SAM9G45-CU datasheet(49/1159 Pages) ATMEL

49 / 1159 page

6438D–ATARM–13-Oct-09

AT91SAM9G45

9.9

Bus Interface Unit

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB

requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables

parallel access paths between multiple AHB masters and slaves in a system. This is achieved by

using a more complex interconnection matrix and gives the benefit of increased overall bus

bandwidth, and a more flexible system architecture.

The multi-master bus architecture has a number of benefits:

• It allows the development of multi-master systems with an increased bus bandwidth and a

flexible architecture.

• Each AHB layer becomes simple because it only has one master, so no arbitration or master-

to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to

support request and grant, nor do they have to support retry and split transactions.

• The arbitration becomes effective when more than one master wants to access the same

slave simultaneously.

9.9.1

Supported Transfers

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or

bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into

packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not

support split and retry requests.

Table 8 gives an overview of the supported transfers and different kinds of transactions they are

used for.

9.9.2

Thumb Instruction Fetches

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses

on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

9.9.3

Address Alignment

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the

necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses

are aligned to word boundaries.

Table 9-7.

Supported Transfers

HBurst[2:0]

Description

SINGLE

Single transfer

Single transfer of word, half word, or byte:

• data write (NCNB, NCB, WT, or WB that has missed in DCache)

• data read (NCNB or NCB)

• NC instruction fetch (prefetched and non-prefetched)

• page table walk read

INCR4

Four-word incrementing burst

Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,

NCB, WT, or WB write.

INCR8

Eight-word incrementing burst

Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.

WRAP8

Eight-word wrapping burst

Cache linefill

AT91SAM9G45-CU Datasheet(PDF) 49 Page - ATMEL Corporation

AT91SAM9G45-CU Datasheet(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL