41 / 89 page
T108 Release
Copyright by Terawins, Inc.
41
3.1.18
VCO & Charge Pump Register
Address Offset:
17h
Access:
Read/Write
Default Value:
48h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
R/W
ADC_VCO
[5:3]
R/W
ADC_ChargePump
[2]
R/W
AutoClampV_B
Reserved for testing
[1]
R/W
AutoClampV_G
Reserved for testing
[0]
R/W
AutoClampV_R
Reserved for testing
3.1.19
Analog Source MUX Selection
Address Offset:
18h
Access:
Read/Write
Default Value:
00h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
RO
Reserved
[5:4]
R/W
AI2SEL (B)
Analog mux selection for ADC channel 2
00: ACB1
01: ACB0
1x: ACB2
[3:2]
R/W
AI1SEL (G)
Analog mux selection for ADC channel 1
00: AY1
01: AY0
1x: AY2
[1:0]
R/W
AI0SEL (R)
Analog mux selection for ADC channel 0
00: ACR1
01: ACR0
1x: ACR2
3.1.20
Y/Cb/Cr Data Switching Control
Address Offset:
19h
Access:
Read/Write
Default Value:
07h
Size:
8 bits
Bit
Access
Symbol
Description
[7:6]
RO
Reserved
[5:4]
R/W
CBINSEL
The digitaized CB or B data can be taken from one of 3 ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
[3:2]
R/W
YINSEL
The digitaized Y or Composite or G data can be taken from one of 3
ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
[1:0]
R/W
CRINSEL
The digitaized CR or Chroma or R data can be taken from one of 3
ADCs:
00: ADC Ch0
01: ADC Ch1
1X: ADC Ch2
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