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T108 Release
Copyright by Terawins, Inc.
87
4.5 I²C Host Interface Timing
Table 4-5 I
2C Host Interface Timing
Parameter
Min
Typ
Max
t1
Bus free time between a Stop and Start condition
4.7us
t2
Hold time (repeated) Start condition
4.0us
t3
Rise time of both SDA and SCL
1000ns
t4
Data hold time
5.0us
t5
Data setup time
250ns
t6
Fall time of both SDA and SCL
300ns
t7
Setup time for a repeated Start condition
4.7us
t8
Setup time for Stop condition
4.0us
tLow
Low period of the SCL
4.7us
tHigh
High period of the SCL
4.0us
fSCL
SCL clock frequency
1Mhz
Cb
Capacitive load for each bus line
400pF
Stop Start
Stop
t1
t2
t3
t4
t5
t6
t7
t8
tLow
tHigh
Figure 4-1 I
2C Timing
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