T108 Release
Copyright by Terawins, Inc.
8
1.7 Pin Description
Table 1-1 Pin Description
Symbol
Pin #
Type
Description
Power Supplies
VDD18
25, 47, 66
PWR
+1.8V digital core power supply
VDD33
37, 60
PWR
+3.3V digital output power supply
AVDDB
3
PWR
+3.3V analog power supply for ADC channel 2
AVDDG
8
PWR
+3.3V analog power supply for ADC channel 1
AVDDR
13
PWR
+3.3V analog power supply for ADC channel 0
VD5A
75
PWR
+5.0V analog power supply for DAC
VD33DAC
84
PWR
+3.3V analog power supply for DAC
VD33PWM
90 or 91(LED)
PWR
+3.3V analog power supply for DC Converter
AVDDP
22
PWR
+1.8V analog power supply for PLL
PVD33
23
PWR
+3.3V analog power supply for PLL
GND
24, 38, 57, 67
GND
Digital ground
AGNDB
7
GND
Analog ground for ADC channel 2
AGNDG
12
GND
Analog ground for ADC channel 1
AGNDR
17
GND
Analog ground for ADC channel 0
VS5A
76
GND
Analog ground for DAC
VS33PWM
91 or 92(LED)
GND
Analog ground for DC Converter
GNDP
18
GND
Analog ground for PLL
PVS33
19
GND
Analog ground for PLL
Output Interface Signals
IOR
79
AO
Channel R current output
IOG
78
AO
Channel G current output
IOB
77
AO
Channel B current output
VCOMAMP
82
AO
VCOM output
VCOMDC
83
AO
VCOM output
VCOM_i
59
DI, P/D
VCOM input
LLCk1
54
DO, P/D Output Data Clock
LLCk2
55
DO, P/D Output Data Clock
LLCk3
56
DO, P/D Output Data Clock
Timing Controller Interface Signals
POL/VCOM
51
DO, P/D Horizontal Polarity Output Signal. Share w/ HSO
STH1
52
DO, P/D Horizontal Start Pulse 1 Signal. Share w/ VSO
STH2
53
DO, P/D Horizontal Start Pulse 2 Signal. Share w/ DEO
Q1H
58
DO, P/D Panel polarity control
LP/OEH
59
DO, P/D Latch pulse for column driver
GCLK/CKV
61
DO, P/D Gate driver clock
GOE/OEV
62
DO, P/D Gate driver output enable
STV1
63
DO, P/D Gate driver start pulse
STV2
64
DO, P/D Gate driver start pulse
Power Management Signals
VEA
85
AO
Error Amplifier output
CSS
86
AO
Soft Start
VFB
87
AI
Feedback of Lamp current
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