DSPIC33FJ32GS608 datasheet(337/416 Pages) MICROCHIP

337 / 416 page

 2009 Microchip Technology Inc.

Preliminary

DS70591B-page 337

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

24.3

BOR: Brown-Out Reset

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the

regulated supply voltage VCAP/VDDCORE. The main

purpose of the BOR module is to generate a device

Reset when a brown-out condition occurs. Brown-out

conditions are generally caused by glitches on the AC

mains (for example, missing portions of the AC cycle

waveform due to bad power transmission lines, or volt-

age sags due to excessive current draw when a large

inductive load is turned on).

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) is applied

before the internal Reset is released. If TPWRT = 0 and

a crystal oscillator is being used, then a nominal delay

of TFSCM = 100 is applied. The total delay in this case

is TFSCM.

The BOR Status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to

operate while in Sleep or Idle modes and resets the

device should VDD fall below the BOR threshold

voltage.

24.4

Watchdog Timer (WDT)

For

dsPIC33FJ32GS406/606/608/610

and

dsPIC33FJ64GS406/606/608/610 devices, the WDT is

driven by the LPRC oscillator. When the WDT is enabled,

the clock source is also enabled.

24.4.1

PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is

32.767 kHz. This feeds a prescaler that can be config-

ured for either 5-bit (divide-by-32) or 7-bit (divide-by-

128) operation. The prescaler is set by the WDTPRE

Configuration bit. With a 32.767 kHz input, the pres-

caler yields a nominal WDT time-out period (TWDT) of

1 ms in 5-bit mode, or 4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>) which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler, time-out periods ranging from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

24.4.2

SLEEP AND IDLE MODES

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the WDT will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

24.4.3

ENABLING WDT

The WDT is enabled or disabled by the FWDTEN

Configuration bit in the FWDT Configuration register.

When the FWDTEN Configuration bit is set, the WDT is

always enabled.

The WDT can be optionally controlled in software when

the FWDTEN Configuration bit has been programmed

to ‘0’. The WDT is enabled in software by setting the

SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user application to enable the

WDT for critical code segments and disable the WDT

during non-critical segments for maximum power

savings.

The WDT flag bit, WDTO (RCON<4>), is not automatically

cleared following a WDT time-out. To detect subsequent

WDT events, the flag must be cleared in software.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

Note:

If the WINDIS bit (FWDT<6>) is cleared, the

CLRWDT instruction should be executed by

the application software only during the last

1/4 of the WDT period. This CLRWDT

window can be determined by using a timer.

If a CLRWDT instruction is executed before

this window, a WDT Reset occurs.

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