DSPIC33FJ32GS608 datasheet(404/416 Pages) MICROCHIP

404 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 404

Preliminary

 2009 Microchip Technology Inc.

APPENDIX B: REVISION HISTORY

Revision A (March 2009)

This is the initial release of this document.

Revision B (November 2009)

The revision includes the following global update:

• Added Note 2 to the shaded table that appears at

the beginning of each chapter. This new note

provides information regarding the availability of

registers and their associated bits

This revision also includes minor typographical and

formatting changes throughout the data sheet text.

All other major changes are referenced by their

respective section in Table B-1.

TABLE B-1:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-Bit Digital

Signal Controllers”

Added “DMA Channels” column and updated the RAM size to 9K for the

dsPIC33FJ64GS406 devices in the controller families table (see Table 1).

Updated the pin diagrams as follows:

• 64-pin TQFP and QFN

- Removed FLT8 from pin 51

- Added FLT8 to pin 60

- Added FLT17 to pin 31

- Added FLT18 to pin32

• 80-pin TQFP

- Removed FLT8 from pin 63

- Added FLT8 to pin 76

- Added FLT19 to pin 53

- Added FLT20 to pin 52

• 100-pin TQFP

- Removed FLT8 from pin 78

- Added FLT8 to pin 93

- Added SYNCO1 to pin 95

Section 4.0 “Memory Organization”

Added Data Memory Map for Devices with 8 KB RAM (see Figure 4-4).

Removed SFRs IPC25 and IPC26 from the Interrupt Controller Register

Map for dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices (see

Table 4-7).

The following bits in the Interrupt Controller Register Map for

dsPIC33FJ32GS406 and dsPIC33FJ64GS406 devices were changed to

unimplemented (see Table 4-7):

• Bit 2 of IFS1

• Bits 9-7 of IFS6

• Bit 2 of IEC1

• Bits 9-7 of IEC6

• Bits 10-8 of IPC4

Removed OSCTUN2 and LFSR, updated OSCCON and OSCTUN,

renamed bit 13 of the REFOCON SFR in the System Control Register

Map from ROSIDL to ROSSLP and changed the All Resets value from

‘0000’ to ‘2300’ for the ACLKCON SFR (see Table 4-56).

Updated bit 1 of the PMD Register Map for dsPIC33FJ64GS608 devices

from unimplemented to C1MD (see Table 4-60).

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