This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.7 / Jun. 2009

1

240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C

This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2

SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb

version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width

form factor of industry standard. It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Part Name

Density

Organization

# of

DRAMs

# of

ranks

Parity

Support

HYMP112P72CP8-C4/Y5/S6/S5

1GB

128Mx72

9

1

O

HYMP125P72CP8-C4/Y5/S6/S5

2GB

256Mx72

18

2

O

HYMP125P72CP4-C4/Y5/S6/S5

2GB

256Mx72

18

1

O

HYMP151P72CP8-C4/Y5/S6/S5

4GB

512Mx72

36

4

O

HYMP151P72CP4-C4/Y5/S6/S5

4GB

512Mx72

36

2

O

HYMP31GP72CMP4-C4/Y5

8GB

512Mx72

72

4

O

HYMP112R72CP8-E3/C4

1GB

128Mx72

9

1

X

HYMP125R72CP4-E3/C4

2GB

256Mx72

18

1

X

HYMP151R72CP4-E3/C4

4GB

512Mx72

36

2

X

•

JEDEC standard Double Data Rate2 Synchro-

nous DRAMs (DDR2 SDRAMs) with 1.8V +/-

0.1V Power Supply

•

All inputs and outputs are compatible with

SSTL_1.8 interface

•8 Bank architecture

•Posted CAS

•

Programmable CAS Latency 3, 4, 5, 6

•

OCD (Off-Chip Driver Impedance Adjustment)

•

ODT (On-Die Termination)

•

Fully differential clock operations (CK & CK)

•

Programmable Burst Length 4 / 8 with both

sequential and interleave mode

•

Auto refresh and self refresh supported

•

8192 refresh cycles / 64ms

•

Serial presence detect with EEPROM

•

DDR2 SDRAM Package: 60 ball(x4/x8)

•

133.35 x 30.00 mm form factor

•RoHS compliant