HYMP31GP72CMP4-C4 datasheet(4/32 Pages) HYNIX

4 / 32 page

Rev. 0.7 / Jun. 2009

240pin Registered DDR2 SDRAM DIMMs

PIN DESCRIPTION

PIN LOCATION

Pin Description

CK0

Clock Input, positive line

ODT[1:0]

On Die Termination Inputs

CK0

Clock input, negative line

VDDQ

DQs Power Supply

CKE0~CKE1

Clock Enable Input

DQ0~DQ63

Data Input/Output

RAS

Row Address Strobe

CB0~CB7

Data check bits Input/Output

CAS

Column Address Strobe

DQS(0~8)

Data strobes

Write Enable

DQS(0~8)

Data strobes, negative line

S0,S1

Chip Select Input

DM(0~8),DQS(9~17)

Data Maskes/Data strobes

A0~A9,A11~A13

Address input

DQS(9~17)

Data strobes, negative line

A10/AP

Address input/Autoprecharge

RFU

Reserved for Future Use

BA0, BA1, BA2

SDRAM Bank Address

No Connect

SCL

Serial Presence Detect (SPD) Clock Input

TEST

Memory bus test tool (Not Connected and Not

Usable on DIMMs)

SDA

SPD Data Input/Output

VDD

Core Power

SA0~SA2

E2PROM Address Inputs

VDDQ

I/O Power Supply

Par_In

Parity bit for the Address and Control bus

VSS

Ground

Err_Out

Parity error found on the Addre

VREF

Reference Power Supply

RESET

Reset Enable

VDDSPD

Power Supply for SPD

CB0~CB7

Data Strobe Inputs/Outputs

pin #1

Front Side

Pin #64

Pin #65

Pin #120

Pin #121

Back Side Pin #184 Pin #185

pin #240

HYMP31GP72CMP4-C4 Datasheet(PDF) 4 Page - Hynix Semiconductor

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