HYMP31GP72CMP4-C4 datasheet(13/32 Pages) HYNIX

13 / 32 page

Rev. 0.7 / Jun. 2009

240pin Registered DDR2 SDRAM DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Note:

Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.

The input signal minimum slew rate is to be maintained over the range from VREF max to VIH(ac) min for rising edges and the

range from VREF min to VIL(ac) max for falling edges as shown in the below figure.

AC timings are referenced with input waveforms switching from VIL (ac) to VIH (ac) on the positive transitions and VIH (ac) to

VIL (ac) on the negative transitions.

Parameter

Symbol

Min

Max

Unit

Note

dc Input logic HIGH

VIH(DC)

VREF + 0.125

VDDQ + 0.3

dc Input logic LOW

VIL(DC)

-0.30

VREF - 0.125

Parameter

Symbol

DDR2 400/533

DDR2 667/800

Unit

Notes

Min

Max

Min

Max

ac Input logic HIGH

VIH(AC)

VREF + 0.250

VREF + 0.200

ac Input logic LOW

VIL(AC)

-VREF - 0.250

VREF - 0.200

Symbol

Condition

Value

Units

Notes

VREF

Input reference voltage

0.5 * VDDQ

VSWING(MAX)

Input signal maximum peak to peak swing

1.0

SLEW

Input signal minimum slew rate

1.0

V/ns

2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

< Figure: AC Input Test Signal Waveform >

VSWING(MAX)

∆TR

∆TF

Start of Falling Edge Input Timing

Start of Rising Edge Input Timing

VREF - VIL(ac) max

∆TF

Falling Slew =

Rising Slew =

VIH(ac) min - VREF

∆TR

HYMP31GP72CMP4-C4 Datasheet(PDF) 13 Page - Hynix Semiconductor

HYMP31GP72CMP4-C4 Datasheet(HTML) 13 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL