AD9148BPCZ datasheet(56/73 Pages) AD

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AD9148

Preliminary Technical Data

Rev. PrA | Page 56 of 73

CLOCK GENERATION

DAC INPUT CLOCK CONFIGURATIONS

The AD9148 DAC sample clock (DACCLK) can be sourced

directly or by clock multiplying. Clock multiplying employs

the on-chip, phased-locked loop (PLL) that accepts a reference

clock (REFCLK_x) operating at a submultiple of the desired

DACCLK rate, most commonly the data input frequency.

The PLL then multiplies the reference clock up to the desired

DACCLK frequency, which can then be used to generate all the

internal clocks required by the DAC. The clock multiplier

provides a high quality clock that meets the performance

requirements of most applications. Using the on-chip clock

multiplier removes the burden of generating and distributing

the high speed DACCLK.

The second mode bypasses the clock multiplier circuitry and

allows DACCLK to be sourced directly through the CLK_x

pins. This mode enables the user to source a very high quality

clock directly to the DAC core. Sourcing the DACCLK directly

through the CLK_x pins may be necessary in demanding

applications that require the lowest possible DAC output noise,

particularly at higher output frequencies.

DRIVING THE CLK_x AND REFCLK_x INPUTS

The REFCLK_x and CLK_x differential inputs share similar

clock receiver input circuitry. Figure 1 shows a simplified circuit

diagram of the input, along with a recommended drive circuit.

The on-chip clock receiver has a differential input impedance of

about 10 kΩ. It is self-biased to a common-mode voltage of about

1.25 V. The recommended circuit for driving the input is a pair

of ac coupling capacitors and a differential 100 Ω termination.

The minimum input drive level to either of the clock inputs is

100 mV ppd. The optimal performance is achieved when the clock

input signal is between 500 mV ppd and 1.6 V ppd. Whether using

the on-chip clock multiplier or sourcing the DACCLK directly,

it is necessary that the input clock signal to the device has low

jitter and fast edge rates to optimize the DAC noise performance.

DIRECT CLOCKING

When a high quality, sample rate clock is connected to the AD9148,

it provides the lowest noise spectral density at the DAC outputs.

To select the differential CLK inputs as the source for the DAC

sampling clock, set the PLL enable bit to 0 (Register 0x0A, Bit 7).

By setting this bit to 0, it powers down the internal PLL clock

multiplier and selects the input from the CLK_x pins as the

source for the internal DACCLK.

The device also has duty-cycle correction circuitry and differential

input level correction circuitry. Enabling these circuits may provide

improved performance in some cases. The control bits for these

functions can be found in Register 0x08.

200Ω

100Ω

5kΩ

1000pF

1.25V

CLK_N/

REFCLK_N

CLK_P/

REFCLK_P

LVPECL

DRIVER

DAC

100Ω

5kΩ

1000pF

1.25V

CLK_N/

REFCLK_N

CLK_P/

REFCLK_P

LVPECL

DRIVER

Figure 71. Clock Receiver Circuitry and Recommended Drive Circuitry using LVPECL (Left) and LVDS (Right)

AD9148BPCZ Datasheet(PDF) 56 Page - Analog Devices

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