P89LPC913 datasheet(35/66 Pages) NXP

35 / 66 page

P89LPC912_913_914_5

Product data sheet

Rev. 05 — 28 September 2007

35 of 66

NXP Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

8.12.3 Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to VDD.

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

8.12.4 Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that

also has a glitch suppression circuit.

8.12.5 Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a Schmitt

triggered input that also has a glitch suppression circuit.

8.12.6 Port 0 analog functions

The P89LPC912/913/914 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-only (high-impedance)

mode as described in Section 8.12.4 “Input-only conﬁguration”.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any

reset, the PT0AD bits default to logic 0s to enable digital functions.

P89LPC913 Datasheet(PDF) 35 Page - NXP Semiconductors