P89LPC913 datasheet(57/66 Pages) NXP

57 / 66 page

P89LPC912_913_914_5

Product data sheet

Rev. 05 — 28 September 2007

57 of 66

NXP Semiconductors

P89LPC912/913/914

8-bit microcontrollers with two-clock 80C51 core

[1]

Parameters are valid over operating temperature range unless otherwise speciﬁed. Parts are tested to 2 MHz, but are guaranteed to

operate down to 0 Hz.

[2]

When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to

hold the device in reset at power-up until VDD has reached its speciﬁed level. When system power is removed VDD will fall below the

minimum speciﬁed operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout

detect circuit may be required to hold the device in reset when VDD falls below the minimum speciﬁed operating voltage.

11.1 Waveforms

tSPIF

SPI fall time

see Figure 26,

27, 28, 29

SPI outputs (SPICLK, MOSI,

MISO)

100

SPI inputs (SPICLK, MOSI,

MISO, SS)

2000

Table 15.

Dynamic characteristics (P89LPC912, P89LPC913) …continued

VDD = 3.0 V to 3.6 V, unless otherwise speciﬁed.

Tamb = −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise speciﬁed.[1]

Symbol

Parameter

Conditions

Variable clock

fosc = 18 MHz

Unit

Min

Max

Min

Max

Fig 24. Shift register mode timing

valid

TXLXL

002aaa906

set TI

set RI

tXHQX

tQVXH

tXHDV

tXHDX

clock

output data

write to SBUF

input data

clear RI

Fig 25. External clock timing

tCHCL

tCLCX

tCHCX

Tcy(clk)

tCLCH

002aaa907

0.2VDD + 0.9 V

0.2VDD − 0.1 V

VDD − 0.5 V

0.45 V

P89LPC913 Datasheet(PDF) 57 Page - NXP Semiconductors

P89LPC913 Datasheet(HTML) 57 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

Datasheet Download

Link URL