M68HC05 datasheet(57/128 Pages) FREESCALE

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Low-Power Modes

Halt Mode

MC68HC05J1A — Rev. 3.0

Technical Data

Low-Power Modes

These conditions restart the CPU clock and bring the MCU out of wait

mode:

•

An external interrupt signal on the IRQ pin — A high-to-low

transition on the IRQ pin loads the program counter with the

contents of locations $07FA and $07FB.

•

An external interrupt signal on a port A external interrupt

pin — If the mask option for the port A external interrupt function

is selected, a low-to-high transition on a PA3–PA0 pin loads the

program counter with the contents of locations $07FA and $07FB.

•

A timer interrupt — A timer overflow or a real-time interrupt request

loads the program counter with the contents of locations $07F8

and $07F9.

•

A COP watchdog reset — A timeout of the mask-optional COP

watchdog resets the MCU and loads the program counter with the

contents of locations $07FE and $07FF. Software can enable

real-time interrupts so that the MCU can periodically exit wait

mode to reset the COP watchdog.

•

External reset — A logic 0 on the RESET pin resets the MCU and

loads the program counter with the contents of locations $07FE

and $07FF.

6.5 Halt Mode

If the mask option to disable the STOP instruction is selected, a STOP

instruction puts the MCU in halt mode. The halt mode is identical to the

wait mode, except that a recovery delay of 1–4064 internal clock cycles

occurs when the MCU exits the halt mode. If the mask option to disable

the STOP instruction is selected, the COP watchdog cannot be

inadvertently turned off by a STOP instruction.

Figure 6-1 shows the sequence of events in stop, wait, and halt modes.

Freescale Semiconductor, Inc.

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M68HC05 Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc