M68HC05 datasheet(69/128 Pages) FREESCALE

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Parallel Input/Output (I/O)

Port B

MC68HC05J1A — Rev. 3.0

Technical Data

Parallel Input/Output (I/O)

7.5.3 Pulldown Register B

All port B pins have mask-optional, programmable pulldown devices that

typically sink 100

µA. Clearing any of the PDIB5–PDIB0 bits in pulldown

Pulldown register B can turn on a port B pulldown device only when the

port B pin is an input. Reset clears bits PDIB5–PDIB0, turning on the port

B pulldown devices.

PDIB5–PDIB0 — Pulldown Inhibit Bits

Writing logic 0s to these write-only bits turns on the port B pulldown

devices. Reading pulldown register B returns undefined data.

1 = Corresponding port B pin pulldown device turned off

0 = Corresponding port B pin pulldown device turned on

Bits 7 and 6 — Not used

NOTE:

Avoid a floating port B input by clearing its pulldown register bit before

changing its DDRB bit from logic 1 to logic 0.

Do not use read-modify-write instructions on pulldown register B.

Figure 7-8 shows the port B I/O logic.

Reading a port B output actually reads the value of the data latch and

not the voltage on the pin itself. When a port B pin is programmed as an

input, reading the port bit reads the voltage level on the pin. The data

latch can always be written, regardless of the state of its DDR bit.

Table 7-2 summarizes the operation of the port B pins.

Address:

$0011

Bit 7

54321

Bit 0

Read:

Write:

PDIB5

PDIB4

PDIB3

PDIB2

PDIB1

PDIB0

Reset:

000000

= Unimplemented

Figure 7-7. Pulldown Register B (PDRB)

Freescale Semiconductor, Inc.

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