HCS12 datasheet(333/452 Pages) FREESCALE

333 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

333

of the IPIPE1 and IPIPE0 pins from their alternate function as mode select

inputs, the status information on these two pins may be erroneous during

the first cycle or two after the release of reset. This is not a problem because

the status is correct in time for queue reconstruction logic to correctly

replicate the queue.

Before starting to reconstruct the queue, clear the is_full flag to indicate that

there is no meaningful information in the fetch_add and fetch_dat buffers.

Further movement of information in the instruction queue is based on the

decoded status on the IPIPE1 and IPIPE0 signals at the rising edges of E.

8.5.2.1 LAT Decoding

On a latch cycle (LAT), check the is_full flag. If and only if is_full = 0, transfer

the address and data from the previous bus cycle (in_add and in_dat) into

the fetch_add and fetch_dat registers, respectively. Then, set the is_full

flag. The usual reason for a latch request instead of an advance request is

that the previous instruction ended with a single aligned byte of program

information in the last stage of the instruction queue. Since the odd half of

this word still holds the opcode for the next instruction, the queue cannot

advance on this cycle. However, the cycle to fetch the next word of program

information has already started and the data is on its way.

8.5.2.2 ALD Decoding

On an advance-and-load-from-data-bus (ALD) cycle, the information in the

instruction queue must advance by one stage. Whatever was in stage 2 of

the queue is simply thrown away. The previous contents of stage 1 are

moved to stage 2, and the address and data from the previous cycle (in_add

and in_dat) are transferred into stage 1 of the instruction queue. Finally,

clear the is_full flag to indicate the buffer latch is ready for new data. Usually,

there would be no useful information in the fetch buffer when an ALD cycle

was encountered, but in the case of a change-of-flow, any data that was

there needs to be flushed out (by clearing the is_full flag).

8.5.2.3 ALL Decoding

On an advance-and-load-from-latch (ALL) cycle, the information in the

instruction queue must advance by one stage. Whatever was in stage 2 of

the queue is simply thrown away. The previous contents of stage 1 are

moved to stage 2, and the contents of the fetch buffer latch are transferred

into stage 1 of the instruction queue. One or more cycles preceding the ALL

HCS12 Datasheet(PDF) 333 Page - Freescale Semiconductor, Inc