HCS12 datasheet(330/452 Pages) FREESCALE

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S12CPUV2 Reference Manual, Rev. 4.0

330

Freescale Semiconductor

8.4.2 Reconstruction Algorithm (for HCS12)

This section describes how to use IPIPE[1:0] signals and queue

reconstruction registers to reconstruct the queue.

Typically, the first few cycles of raw capture data are not useful because it

takes several cycles before an instruction propagates to the head of the

queue. During these first raw cycles, the only meaningful information

available is data movement signals. Information on the external address

and data buses during this setup time is still captured and propagated

through the reconstructed queue, but the information reflects the actions of

instructions that were fetched before data collection started.

In the special case of a reset, there is a five-cycle sequence (VfPPP) during

which the reset vector is fetched and the instruction queue is filled, before

execution of the first instruction begins. Due to the timing of the switchover

of the IPIPE[1:0] pins from their alternate function as mode-select inputs,

the status information on these two pins may be erroneous during the first

cycle or two after the release of reset. This is not a problem because the

status is correct in time for queue reconstruction logic to correctly replicate

the queue.

On an advance-and-load-from-data-bus (ALD) cycle, the information in the

instruction queue must advance by one stage. Whatever was in stage three

of the queue simply disappears. The previous contents of stage two go to

stage three, the previous contents of stage one go to stage two, and the

contents of fetch_add and data from the current cycle go to stage one.

Figure 8-3 shows the reset sequence and illustrates the relationship

between instruction cycle codes (VfPPP) and pipe status signals. One cycle

of the data bus is shown to indicate the relationship between the ALD data

movement code and the data value it refers to. The SEV execution start

code indicates that the reset vector pointed to an even address in this

example.

Figure 8-3. Reset Sequence for HCS12

ALD

SEV

INSTRUCTION

CYCLE CODES

E CLOCK

DATA BUS

IPIPE[1:0]

FIRST

USER

INSTRUCTION

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